A 4.9-GHz low power, low jitter, LC phase locked loop
نویسندگان
چکیده
منابع مشابه
A 4.9-GHz Low Power, Low Jitter, LC Phase Locked Loop
This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-μm Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5 ps, respectively. The measured tuning range, from 4.6 to 5.0 GHz, is narrower than the expected one, from 3.8 to 5.0 GHz. The narrow tuning range issue has b...
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ژورنال
عنوان ژورنال: Journal of Instrumentation
سال: 2010
ISSN: 1748-0221
DOI: 10.1088/1748-0221/5/12/c12045